1. Field of the Invention
The invention relates in general to a reading method and a reading circuit, and more particularly to a reading method for a multi-level cell (MLC) memory and a reading circuit using the same.
2. Description of the Related Art
Non-volatile memories are widely used in various products, such as mobile phones, digital cameras and personal digital assistants (PDAs). The non-volatile memories may be classified into various kinds, one of which is the multi-level cell memory that is frequently seen.
FIG. 1 is a structure diagram showing a conventional MLC memory cell 100. Referring to FIG. 1, the MLC memory cell 100 includes a left half cell 110 and a right half cell 120. Each half cell can trap charges, and the amount of trapped charges influences the threshold voltage states of each half cell so that the object of storing data can be achieved. That is, the data content stored in each half cell can be obtained according to the threshold voltage states of each half cell. Furthermore, in an MLC memory having many MLC memory cells 100, the threshold voltages of the MLC memory cells 100 are not completely the same even if the same data is stored in the MLC memory cells 100 because the physical properties of the MLC memory cells 100 are not completely the same. So, the states of each half cell are represented by the threshold voltage distribution.
FIG. 2 is a schematic illustration showing one example of threshold voltage distribution of the MLC memory. As shown in the example of FIG. 2, it is assumed that each half cell can store 2 bits of data. Thus, the threshold voltage distribution of the MLC memory having a number of MLC memory cells 100 has four threshold voltage states {11, 10, 00, 01}. Taking the threshold voltage state {11} corresponding to the left half cell as an example, the threshold voltage state {11} represents that the threshold voltage value of the left half cell ranges between 2.0 to 3.1 volts. The threshold voltage state {11} represents that the data value stored in the left half cell is “11”.
Conventionally, when the reading operation is being performed, different word line voltages are applied to a gate G of the MLC memory cell 100, corresponding bit line voltages are applied to the source or drain of the MLC memory cell 100, and the data value stored in the MLC memory cell 100 is judged according to the value of the current flowing through the source S. As shown in FIG. 2, when the data of the MLC memory cell is read, the used word line voltage is at least one of the word line voltages VG1 to VG3. For example, the level of the word line voltage VG1 ranges between the threshold voltage states {01} and {00}, that is, ranges between 4.7 and 5.5 volts.
When the MLC memory cell is being read, a subsequent read error may be caused due to read disturb. FIG. 3 is a schematic illustration showing the conventional MLC memory cell 100 encountering the read disturb. Referring to FIGS. 3 and 2, the charges stored in the right half cell 120 are influenced when the MLC memory cell 100 is being read. That is, the operation of reading the left half cell 110 influences the threshold voltage value of the right half cell 120 because the word line voltage VG and the bit line voltage VBL used to read the left half cell 110 approach the word line voltage VG and the bit line voltage VBL used to program the right half cell 120.
More particularly, when the threshold voltage of the left half cell 110 pertains to the threshold voltage state {01} and the threshold voltage of the right half cell 120 pertains to the threshold voltage state {11} and when the left half cell 110 is being read, the right half cell 120 is influenced most seriously. Therefore, the problem of the read error may occur if the data stored in the right half cell 120 is to be read after the left half cell 110 is read.
Thus, it is an important subject in the industry to avoid the above-mentioned read disturb, to avoid the problem of the stored data error caused by the threshold voltage values of the neighboring half cells, and to increase the correctness of reading the MLC memory.